This invention relates to a pattern generator for a semiconductor integrated circuit tester.
A conventional semiconductor integrated circuit (IC) tester has a separate channel for each pin of a device under test (DUT). A typical tester channel includes a pin electronics circuit having a tester pin which engages a pin of the DUT. The tester organizes an IC test into a succession of test cycles, and during each test cycle, each channel uses its pin electronics circuit either to send a stimulus signal to its DUT pin or to monitor a response signal at the DUT pin to determine if the DUT is behaving as expected.
Operation of the tester is controlled by a host computer which generates, for each test cycle, a test pattern for each channel. Typically, the test pattern is a 4-bit word. The test pattern is supplied to the pin electronics circuit to establish the state of the pin electronics circuit on the next test cycle. The typical test channel also includes a test pattern memory into which the test patterns are loaded prior to test execution and a sequencer which generates a sequence of addresses for reading the test patterns from the test pattern memory and supplying the test patterns to the pin electronics circuit in the proper order.
Traditionally, the test pattern memory has been implemented using SRAM. However, Saito, U.S. Pat. No. 5,265,102, shows a test pattern generator for a semiconductor integrated circuit tester in which the test pattern memory is implemented using DRAM. Use of DRAM in the test pattern memory is advantageous because it is less expensive than SRAM. However, DRAM is subject to the disadvantage that the contents of the DRAM must be refreshed and readout of the test pattern must be suspended during the refresh interval. Accordingly, in order to accommodate use of DRAM to implement the test pattern memory, the test patterns are read from the DRAM in blocks of several test patterns at a time. The blocks are temporarily stored in an interface circuit, such as a FIFO memory, and are supplied to the pin electronics circuit in the proper order and with the proper timing.
An error can be induced in the data stored in a DRAM chip by interaction with alpha particles generated in the DRAM packaging material. The data remains incorrect until the correct data is rewritten by reloading the memory with the proper test pattern data from the host computer. This type of error is known as a soft error. The probability of occurrence of a soft error in a single DRAM chip is quite small. However, if a semiconductor integrated circuit tester uses a relatively large number of DRAM chips for the test pattern memory, soft errors can become statistically significant. For example, if the tester has 512 device pins and four DRAM chips per device pin, the tester includes over 2,000 DRAM chips. If each DRAM chip has a single bit soft error rate of 94 failures per billion hours of operation, reasonably conservative calculations show that there is approximately a 3 percent per day probability of incurring a soft error.
Since soft errors in DRAMs are caused by random external events, the frequency with which the correct memory data is loaded into the DRAM does not affect the probability of a soft error, although it may affect its impact.
Many IC testers are used in a production environment, in which a test pattern is loaded into the test pattern memory followed by days of test program execution. An undiscovered error in a test pattern could compromise the test results for an entire production run of integrated circuit devices. If there is a significant change in device yield, the operator may recognize the possibility of a soft error and take suitable remedial action, such as reloading the test pattern memory and retesting devices. However, a soft error might cause a small change in device yield, which might not be noticed. In this case, faulty devices may be classified as good and shipped to customers, or good devices may be classified as faulty and discarded as scrap.